1. Technical Field
The present disclosure relates to a method of forming electrical-contact interface regions of an electronic device. In particular, the present disclosure is directed to formation of nickel-silicide electrical-contact interface regions; in particular, the nickel-silicide regions are formed on a silicon-carbide substrate.
2. Description of the Related Art
As is known, semiconductor materials that have a wide bandgap, in particular that have a value of energy Eg of the bandgap higher than 1.1 eV, low resistance in the ON state (RON), high value of thermal conductivity, high operating frequency, and high value of saturation of the speed of the charge carriers, are ideal for providing electronic components, such as, for example, transistors or switches, in particular for power applications. A material having said characteristics, and designed to be used for manufacturing electronic components, is silicon carbide (SiC). In particular, silicon carbide, in its different polytypes (for example, 3CSiC, 4H—SiC, 6H—SiC), is preferable to silicon as regards the properties listed previously.
Electronic devices made on a silicon-carbide substrate, as compared to similar devices made on a silicon substrate, possess a plurality of advantageous characteristics, such as, for example, a low output on-resistance, a low leakage current, a high working temperature, and high working frequencies.
A significant technological problem, encountered during steps for manufacturing electronic devices based upon SiC, regards structural defects observed following upon steps of formation of metal contacts used for supplying the appropriate electrical signals for biasing and/or control of said electronic devices (for example, for forming contacts of the source and drain terminals in the case of a transistor), as illustrated in the example of FIGS. 1-4.
With reference to FIG. 1, a wafer houses an electronic device (for example, a MOSFET), of a known type, and comprises: a semiconductor body 1, made of silicon carbide, having a P conductivity; a first conductive region 5 and a second conductive region 6 (source and drain, respectively), which extend in the semiconductor body and have a second type of conductivity (N); and an insulated-gate region 3 set on top of the semiconductor body 1, between the first and second conductive regions 5, 6. The gate region 3 comprises a dielectric layer 3a, in direct contact with the semiconductor body 1 and a conductive region 3b, set on top of the dielectric region 3a. 
The semiconductor body 1 is insulated from the outside world by means of an insulating layer 7, which extends over the first and second conductive regions 5, 6 and the gate region 3. The first and second conductive regions 5, 6 are electrically accessible from the outside of the electronic device by means of respective metal contacts 8, 9 (in particular, the metal used is nickel), which extend through the insulating layer 7. The interface regions 13, between the first and second conductive regions 5, 6 and each respective metal contact 8, 9, are nickel-silicide regions Ni2Si that provide the electrical connection between the first and second conductive regions 5, 6 and the respective metal contact 8, 9.
FIG. 2 shows the wafer comprising the electronic device of FIG. 1 in an intermediate manufacturing stage, in particular for the formation of the nickel-silicide regions 13.
In this case, formed on the semiconductor body 1 (housing the first and second conductive regions 5, 6) is a dielectric layer 10, of deposited silicon oxide or TEOS silicon oxide, having a thickness of between 0.5 μm and 2 μm. The dielectric layer 10 is then selectively etched using a photoresist mask 14 so as to form in the dielectric layer 10 openings 11 that expose the surface of the underlying semiconductor body 1. The openings are formed in the area of the first and second conductive regions 5, 6. In general, openings similar to the openings 11 are formed in the dielectric layer 10 wherever it is useful to form metal contacts.
Then (FIG. 3), the photoresist mask 14 is removed, and a metal layer 12, in particular a nickel layer, is formed on the dielectric layer 10 and on the surface of the semiconductor body 1, exposed via the openings 11. The metal layer 12 is deposited by means of the sputtering technique. A subsequent thermal process comprising a rapid thermal annealing (RTA) at a temperature of between 700° C. and 1100° C. for some minutes enables formation of the nickel-silicide regions 13 in the regions of direct contact between the semiconductor body 1 and the metal layer 12.
Then (FIG. 4), the metal layer 12 is etched, for example, using a solution of nitric acid HNO3, to remove it from the wafer except for the nickel-silicide regions. Etching with nitric acid is selective with respect to silicide, which is not removed.
Moreover, also the dielectric layer 10 is removed, by means of a masked etch using hydrofluoric acid (HF).
The present applicant has found that the high temperatures used for the RTA step cause a reaction between the nickel of the metal layer 12 and the silicon oxide of the dielectric layer 10 such that there is formation of a thin interface layer between the dielectric layer 10 and the metal layer 12. This interface layer is (from XPS analysis) a matrix of nickel silicide, nickel oxide, nickel hydroxide, silicon oxide, and nickel atoms. Consequently, the step of etching with nitric acid HNO3 of the metal layer 12 does not enable convenient removal also of the interface layer. A complete removal of the interface layer is possible by prolonging over time the step of etching with nitric acid HNO3. The etching step can be prolonged over time by a factor of 6 or more.
The present applicant has likewise found that, following upon complete removal of the metal interface layer, the dielectric layer 10 presents a damaged surface. The damage of the dielectric layer 10 is an undesirable effect.
A possible solution to this problem comprises depositing, by means of sputtering, the metal layer 12 directly on the semiconductor body and then carrying out a masked etch of the metal layer 12 so as to remove the latter in the area of portions of the surface of the semiconductor body 1 in which it is not desired to form the nickel-silicide regions. The step of removal of the metal layer 12 can be performed by means of dry etching or wet etching. Dry etching of the metal layer 12, however, has revealed a poor selectivity in so far as, in addition to the metal layer 12, also oxides and/or other dielectrics present on the wafer are removed. Wet etching, instead, does not enable definition of the metal layer 12 with the desired precision, on account of the different rate of etching observable along planes parallel to the direction of etching with respect to planes orthogonal to the direction of etching.
Moreover, the step of removal of the dielectric layer 10 with hydrofluoric acid HF causes damage to the nickel silicide. In fact, typically, the layout of the devices in question do not enable formation of a mask that will cover also the parts where the silicide has already been formed.